The present invention relates to switching regulator circuits. More particularly, the present invention relates to circuits and methods for maintaining constant amounts of slope compensation in switching regulators preferably independent of variations of switching frequency of the regulators.
The purpose of a voltage regulator is to provide a predetermined and substantially constant output voltage to a load from a voltage source which may be poorly-specified or fluctuating. Two types of regulators are commonly used to provide this function; a linear regulator and a switching regulator. In a typical linear regulator, the output voltage is regulated by controlling the flow of current through a pass element from the voltage source to the load.
In switching voltage regulators, however, the flow of current from the voltage source to the load is not steady, but is rather in the form of discrete current pulses. To create the discrete current pulses, switching regulators usually employ a switch (such as a power transistor) that is coupled either in series or parallel with the load. The current pulses are then converted into a steady load current with an inductive storage element.
By controlling the duty cycle of this switch—i.e., the percentage of time that the switch is ON relative to the total period of the switching cycle—the switching voltage regulator can regulate the load voltage. In current-mode switching voltage regulators—i.e., a switching regulator that is controlled by a current-derived signal in the regulator—there is an inherent instability when the duty cycle exceeds 50%—i.e., when the switch is ON for more than 50% of a given switching period. Stability is often maintained in such current-mode switching regulators by adjusting the current-derived signal used to control the regulator with a slope compensation signal which compensates for the instability present at higher duty cycles. From the slope compensation theory it is generally known that the slope compensation signal is only needed at the instant when the switching regulator switch turns OFF
One method of producing such a slope compensation signal is to use a portion of an oscillator signal as the compensation signal. The oscillator signal may be, for example, a ramp signal that is used to generate a clock signal that controls the switching of the regulator. The slope compensation signal can be applied by either adding the ramp signal to the current-derived signal, or by subtracting it from a control signal. By deriving the slope compensation signal from a signal that oscillates the switch of the regulator, the slope compensation signal is synchronized with the switching of the regulator.
In the conventional current mode switching regulator 100 shown in FIG. 1, slope compensation is needed for the operating duty cycle of 50% or higher to avoid sub-harmonic oscillation. Switching regulator 100 preferably includes oscillator 102, flip-flop 104, preferably pulse width modulated switch control circuit 106, inductor 108, resistor divider formed from resistors 110 and 112, output capacitor 114, output load 116, voltage feedback (or other suitable type, such as current feedback, of) amplifier 118, feedback capacitor 120, and current comparator 122 which is adapted to receive a switch current sample 126 and a slope compensation signal 124 and to compare the sum of these signals with a signal from voltage feedback amplifier 118.
This exemplary circuit uses a common type of switching regulator which is known as a pulse-width modulation (PWM) regulator. The PWM regulator relies on pulse width modulation to produce output signals of different amplitudes. PWM switching regulators vary the duty-cycle of the output signals they produce in order to adjust the current supplied and the voltage level maintained at their output or outputs. The voltages supplied at the outputs of these regulators may depend on the ratio of the switch pulse width to the switch pulse period, a higher ratio producing a higher output voltage.
Oscillator 102 is shown in greater detail in FIG. 2 as oscillator 200. Oscillator 200 preferably includes a charging source 202 for charging oscillator capacitor 204, an oscillator switch 206, an oscillator current comparator 208, a discharging current sink 210 for discharging oscillator capacitor 204, and a second comparator 212 that provides the Vset signal to voltage regulator 100 (not shown in FIG. 2.)
Typically, regulators use the oscillator voltage Vramp, derived in the circuit shown in FIG. 2 and depicted as the signal 300 shown in FIG. 3A, as a reference to generate the slope compensation. Vset indicates the low and high signals, T1 and T2, respectively, that are transmitted to flip-flop 104 of voltage regulator 100.
FIG. 4A shows compensation curve Sx 402 with a selected portion of Vramp 404. The x-axis of FIG. 4A shows the duty cycle of the switching regulator. The y-axis runs from 0 volt to 1 volt. In order to generate slope compensation curve Sx 402, conventional switching regulators use the circuit shown in FIG. 4B. This circuit includes unity gain buffer 406, NPN transistor 408 and resistor 410.
Linear slope compensation curve Sx 402 typically starts at 50% duty cycle (as shown in FIG. 4A) and is determined by VB. In one particular case, VB may be equal to 0.5V (arbitrarily chosen). Furthermore, Sx 402 has a fixed slope determined by resistor 410.
The oscillator ramp Vramp is fed to the positive input of unity gain buffer 406 and VB and resistor 410 are connected to the negative input. Only when Vramp is higher than VB does NPN transistor 408 turn ON. The emitter current of transistor 408 is determined by:
      Vramp    -    VB        Res    ⁢    .410  This emitter current of transistor 408 forms the slope compensation signal Sx 402.
VB determines slope compensation curve Sx 402 starting point Ts as follows:
            Ts      ⁢                          ⁢              (                  Sx          ⁢                                          ⁢          Starting          ⁢                                          ⁢          point                )              =          VB              Vpeak        ⁢                                  ⁢        of        ⁢                                  ⁢        Vramp              ⁢        and resistor 410 determines the slope of the curve, as shown below:
      Slope    ⁢                  ⁢    of    ⁢                  ⁢    Sx    ⁢                  ⁢    402    ⁢          :        ⁢                  ⁢                  ⅆ        Sx                    ⅆ        t              =            ⅆ      Vramp              Resistor      ⁢                          ⁢      410      ⁢                          ⁢      x      ⁢                          ⁢              ⅆ        t            Because Vramp is a linear ramp, VB is therefore directly proportional to the duty cycle. In one exemplary system, when VB=0.5, Ts corresponds to a 50% duty cycle from the foregoing equations.
One problem associated with the exemplary prior art configuration is that, because the slope compensation curve starts at 50%, it builds up to a very high level Smax at maximum duty cycle 100%.
This high level Smax can cause problems when the regulator is operating at a high duty cycle as follows. Because VC (shown as the output of feedback amplifier 118) at current comparator 122 positive input generally has the same value as the sum of the switch current sample and the slope compensation signal at the negative input of current comparator 122 when the regulator loop closes, it is often used to indicate the output current load level. But at a high duty cycle, the slope compensation builds up from 50% duty cycle and introduces high offset at VC, and VC will not accurately indicate true output load current. Because of this high offset at high duty cycle, problems include a reduced current limit level. This problem is especially pertinent if a fixed VC level is used for current limit. Furthermore, a highly efficient Burst Mode™ threshold will be off at light load situations if a fixed VC level is used to determine the Burst Mode™ threshold.
Another problem associated with the prior art is that the circuit has to use very high current to generate this high level slope compensation signal when operating at high duty cycle.
Therefore, it would be desirable to provide a slope compensation signal that does not cause the voltage regulator circuit to lose the indication of true output load current at high duty cycles.
It would also be desirable to limit the current required to generate a high level slope compensation signal at high duty cycles.